The present invention relates to the testing of chips or other devices and to the diagnosing of faults on those chips or devices, for example in analog or radio frequency (RF) circuits.
In a known method, the circuit behavior is simulated for each possible fault under each relevant combination of process parameters and stored in a fault dictionary. The measurements of a diagnosed circuit or device under test (DUT) are compared to all entries in the fault dictionary, wherein the most similar entry of the fault dictionary identifies the diagnosed fault. This method is straightforward, but involves a large number of long running simulations. Furthermore, it involves modeling of the test conditions. An example is described by F. Liu, S. O. Ozev: “Efficient Simulation of Parametric Faults for Multi-Stage Analog Circuits”, ITC 2007.
The ability to diagnose faults is essential for yield learning, for example, improving the yield during production, but corrective action is only possible when the physical nature of a fault is known. In contrast to fault diagnosis for digital systems, no practical method is known for faults that expose themselves as parametric variation, for example, in analogue or radio frequency (RF) circuits.